1. Field of the Invention
The present invention relates to a laminated semiconductor substrate for manufacturing a laminated chip package including a plurality of laminated semiconductor chips, a laminated chip package and a method of manufacturing the same.
2. Related Background Art
In recent years, electronic devices such as cellular phones and notebook personal computers need to be reduced in weight and improved in performance. With such needs, higher integration of electronic components used for the electronic devices has been required. Further, the higher integration of electronic components has been required also for increase in capacity of a semiconductor memory device.
Recently, System in Package (hereinafter referred to as a “SIP”) has attracted attention as a highly integrated electronic component. The SIP is a device created by stacking a plurality of LSIs and mounting them in one package, and a SIP using the three-dimensional mounting technique of laminating a plurality of semiconductor chips has received attention recently. Known as such a SIP is a package having a plurality of laminated semiconductor chips, that is, a laminated chip package. The laminated chip package has an advantage that speed up of operation of circuits and reduction in stray capacitance of wiring become possible because the length of the wiring can be reduced as well as an advantage of capability of high integration.
Known as the three-dimensional mounting techniques for manufacturing the laminated chip package include a wire bonding system and a through electrode system. The wire bonding system is a system of laminating a plurality of semiconductor chips on a substrate and connecting a plurality of electrodes formed on each of the semiconductor chips and external connecting terminals formed on the substrate by wire bonding. The through electrode system is a system of forming a plurality of through electrodes in each of the laminated semiconductor chips and realizing wiring between the respective semiconductor chips by the through electrodes.
The wire bonding system has a problem of a difficulty in reducing the spaces between the electrodes in a manner that the wires are not in contact with each other, a problem of a difficulty in speeding up the operation of circuits because of a high resistance value of wires, and a problem of a difficulty in reducing the thickness.
Though the above-described problems in the wire bonding system are solved in the through electrode system, the through electrode system has a problem of increased cost of the laminated chip package because many processes are required for forming the through electrodes in each of the semiconductor chips.
Conventionally as methods of manufacturing the laminated chip package, for example, techniques disclosed in Japanese Patent Application Laid-Open No. 2003-163324 (referred also to as patent document 1), Japanese Patent Application Laid-Open No. 2003-7909 (referred also to as patent document 2), Japanese Patent Application Laid-Open No. 2008-187061 (referred also to as patent document 3), Japanese Patent Application Laid-Open No. 2007-234881 (referred also to as patent document 4) are known.
The patent document 1 discloses a laminated-type semiconductor device in which a plurality of layers of unit semiconductor devices having identical semiconductor chips are laminated. In the laminated-type semiconductor device, an insulating resin layer with through holes is formed around the semiconductor chips. In the through hole, a wiring plug is formed. The wiring plug extends from the front surface to the rear surface of the semiconductor chip, and an external electrode is connected to the front surface. Further, a wiring pattern is connected to the rear surface. One wiring pattern is formed for each laminated-type semiconductor device, and another wiring pattern is formed across adjacent laminated-type semiconductor devices to be shared between the adjacent laminated-type semiconductor devices (see FIG. 1, FIG. 2 and so on).
Besides, the patent document 2 discloses a laminated-type semiconductor device having a structure in which a plurality of semiconductor devices having through electrodes which reach the rear surface from the front surface provided therearound are laminated (see FIG. 47). The patent document 3 discloses a laminated memory in which a plurality of memory chips having through holes formed inside the peripheral edge part are laminated (see FIG. 6 and so on). Furthermore, the patent document 4 discloses a semiconductor device in which semiconductor substrates having through electrodes formed inside the peripheral edge part are laminated (see FIG. 2 and so on).